We propose a high-level configurable description language that automatically synthesizes into IP core designs. The architecture of this system leverages the programability of SystemVerilog but extends it with a high level of mathematical abstraction. It allows the hardware designer to specify algorithms and constraints in their designs directly, without concerns about the unnecessary details of hardware ctions when developing larger IPs. Our two-level compiler automatically translates a high level abstraction into a paramterized template,which ter with user input on the choices of the parameters,synthesizes to a custom RTL. This architecturegeneralizes the Spiral system to handle more diverse design problems than DSP and uses a frontend familiar to most hardware engineers. More importantly, the interactive parameter instantiation approach conveniently exposes areas of algorithmic optimization to the designer and automatically.


Figure 1: The architecture